Beratungs- und Designleistungen fuer Design-for-Test (DFT) und funktionale Verifikation von Mikrochips

The following tasks are initially planned: • Setup of verification environment, server and simulation tool infrastructure • Familiarization with the design functionalities algorithms, structure and design hierarchy • Setup of test plans for hierarchical block level verification with UVM • Continuous development of testcases and execution of simulations, analysis and documentation of the verification results, support of bug fixing with the IIS design team • The progress and results of the described tasks will be the starting point for the definition of the following work III. Essential requirements • At least 10 years of experience in digital functional verification • At least 10 years of experience using standard functional verification and simulation tools from major providers like Synopsys, Cadence or Siemens-Mentor • At least 10 years of experience of setting up and use of verification environments and regression suites • Deep knowledge and experience in UVM verification methodology • Excellent analysis and documentation skills • Business fluent in German and English

The following tasks are initially planned: • Setup of DFT environment for implementation and simulation with Cadence or Siemens EDA depending on the projects requirements o E.g. JTAG, MBIST, SCAN,… • Defining a DFT strategy for the individual projects • Familiarization with the project’s functionality, structure and design hierarchy • Continuous and iterative improvement of the test coverage • The progress and results of the described tasks will be the starting point for the definition of the following work III. Essential requirements • At least 10 years of experience in complex digital Design-for-Test • At least 10 years of experience in developing a proper Test strategy with Frontend Designers • In-depth knowledge about the different Test capabilities • Excellent analysis and documentation skills • Business fluent in English, German is a plus